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Design and implementation of 4-bit flash ADC using folding technique in cadence tool
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ABSTRACT In this paper, we design a pipelined flash Analog-to-Digital Converter (ADC) to achieve high speed using 0.18 umCMOS technology. The results obtained are also presented here. The physical circuit is more compact than the previous design. Power,

Calculation of power consumption in 7 transistor SRAM cell using cadence tool
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ABSTRACT In this paper a new 7T SRAM is proposed. CMOS SRAM Cell is very less power consuming and have very less read and write time. In proposed SRAM an additional write bit line balancing circuitry is added in 6T SRAM for power reduction. A seven Transistor (7T)

Design of CMOS LNA for radio receiver using the cadence simulation tool
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First we design the Common LNA and Cascode LNA in Cadencetool separatelyFigure 8: Common LNA Schematic First we design the Common gate amplifier using the cadence tool shows gate as an input signal and drain as an output signal

Implementation and Analysis of SC-LECTOR CMOS Circuit Using Cadence Tool
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Abstract: In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chiptotal power consumption. We propose a technique called SC-LECTOR which combines leakage control techniques applied at

Mapping of 4-Bit Array Multiplier using Cadence Tool for Low Power High Speed
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Abstract: Now a days, low power Very Large Scale Integration (VLSI) circuit plays an important role in designing efficient energy saving electronic systems for high speed performance. In this, low power consumption is one of the most important criteria in various

Performance Analysis of Current Starved VCO in CMOS 45 nm process Technology using Cadence Tool
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Current Starved Voltage Controlled Oscillators (CSVCO) using 45nm CMOS technology. Voltage Controlled Oscillators can be built using a vast number of circuit techniques. The design and implementation of the proposed is performed using Cadence CAD (Computer

Custom Digital Design of High Speed 8 Bit Multiplier Using Cadence Tool
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Abstract Many digital systems, comprising computers, necessitate implementation of integer and/or floating point multiplication and division. Further, numerous of these applications expect that multiplication and division for operands of significant size be performed at very

Design of a Low Power Flip-flop Using MTCMOS Technique in Cadence Tool
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Flip-Flops having less number of transistors and only one transistor being clocked by short pulse train which is true single phase clocking (TSPC) Flip-Flop. MTCMOS is one of the most important low power techniques which effectively reduce the leakage power. The MTCMOS

Critical-Path Realization and Implementation of the LMS Adaptive Algorithm Using Verilog-HDL and Cadence Tool
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Abstract: This paper introduces a brief description about Critical path realization of the Least Mean Square (LMS) adaptive filter and modified Delayed Least Mean Square (DLMS) adaptive filter to achieve a lower adaptation delay. To achieve lower adaptation delay, it is

High Performance 64-bit Error Tolerent Adder Using Cadence Tool
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Abstract In the conventional adder circuit, the delay is mainly attributed to the carry propagation chain along the critical path, from the least significant bit (LSB) to the most significant bit (MSB). Also glitches in the carry propagation chain dissipate a significant

Design and Analysis of Low Power Phase Locked Loop Based Frequency Synthesizer using Cadence Tool
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Abstract-The CMOS PLL based Frequency Synthesizer is a vital role in Receiver front end Sub component. The main objective of this paper is to design a high frequency of oscillation, less phase noise and power efficient PLL. In general, the PLL contains PFD, Loop Filter,

An Improved 6-T Sram with Low Power Utilization and Implementation In Cadence Tool
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ABSTRACT A new approach for 6-T sram to avoid defects of old 6T sram and it is giving the results nearer to 8T sram. I just gave the different bit line which makes the old 6T sram defective to perfect working condition in terms of Average power and Delay. The cadence

Modeling and designing of Sense Amplifier based Flip-Flop using Cadence tool at 45nm
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ABSTRACT-Today to compete the race of improvements and advancements of technological mysteries are lasting upon innovative ideas and noble thoughts. The consequences of using normal Master-Slave Flip-flops in ultra high speed circuits are

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Abstract: This paper shows a low power and High Speed bypassing multiplier. The essential power decreases are gotten by tuning off MOS parts through multiplexers when the operands of multiplier are zero. The multiplier embraces ripple-carry adder with less extra

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