ic-component-charge pump

charge pump

charge pumps circuits are widely used in integrated circuits (ICs) devoted to several kind of applications such as smart power, nonvolatile memories, switched capacitor circuits, operational amplifiers, voltage regulators, SRAMs, LCD drivers, switching regulator that delivers the power by only charging and discharging capacitors. It’s suitable for application that has low currents and has moderate input to output voltage difference. The advantage of using charge pump regulator is that it has no inductor in the regulator. a kind of DC to DC converter that uses capacitors for energetic charge storage to raise or lower voltage. Charge-pump circuits are capable of high efficiencies,

A high efficiency charge pump for low voltage devices
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Abstract A charge pump is a kind of DC to DC converter that uses capacitor as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. Charge

A Phase Frequency Detector and Charge Pump For DPLL Using 0.18m CMOS Technology
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AbstractThis paper presents a Low power phase frequency detector with charge pump for low power phase lock loop. The phase frequency detector with dead zone compensation has been proposed. The paper contains the detailed circuit diagram of PFD and charge

Double and triple charge pump circuit for a smart power device
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This paper propose a study on a drive method ( charge pump ) of a Power MOS used as switch. The problem is theretically analysed developping two models valid for two different circuital topology. The results are verified performing the tests on a drive circuit which is a

A dickson charge pump with gate drive enhancement and area saving
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Abstract This paper presents a novel charge pump scheme, which combines the advantages of Fibonacci and Dickson charge pumps together, to obtain 30 V voltage for display driver IC application. This design only needs four external capacitors, which is more suitable for

High Current Matching over Full-Swing and Low-Glitch Charge Pump Circuit for PLLs
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Abstract. A high current matching over full-swing and low-glitch charge pump (CP) circuit is proposed. The current of the CP is split into two identical branches having one-half the original current. The two branches are connected in source-coupled structure, and a two-

A 1-GHz charge pump PLL frequency synthesizer for IEEE 1394b PHY
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Abstract The design procedure of an 1-GHz phase-locked loop (PLL)-based frequency synthesizer used in IEEE 1394b physical (PHY) system is presented in this paper. The PLL loop dynamics are analyzed in depth and theoretical relationships between all loop Abstract: A novel chargc putlip system sharing the coupling capacilors for NOR architecture flash memory is propod m ttus paper. Two charge punips operating altematively can share the coupling capacitors. With the proposed technique. the chip sue of the charge puny circuit

Design and Implementation of low power Dickson Charge Pump in 0.18 um CMOS Process
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Abstract Charge pump circuits are used to obtaining higher voltages than normal power supply voltages in low voltage Phase Lock Loop (PLL), flash MemoriesDRAM . New integrated Dickson Charge pump design with charge transfer switches (CTS ) is optimized

Novel CMOS Bulk-driven Charge Pump for Ultra Low Input Voltage
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Abstract. In this paper, a novel bulk-driven cross-coupled charge pump designed in standard 90 nm CMOS technology is presented. The proposed charge pump is based on a dynamic threshold voltage inverter and is suitable for integrated ultra-low voltage converters. Due to a

A dual compensated charge pump with reduced current mismatch
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Abstract:-The charge pump in a phase-locked loop is a key element in determining reference spurs of the VCO output signal. To reduce reference spurs, the current mismatch in the charge pump must be minimized. This paper presents a dual compensation method to

Simple design of an ultra-low-ripple DC/DC boost converter with TPS60100 charge pump
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Battery-powered equipment uses DC/DC step-up converters to generate supply voltages for internal circuits that require higher voltages than the available battery voltage. These can be inductive or capacitive converters. Inductive step-up converters, also called boost

Modification of the Cockcroft-Walton charge pump by using switched capacitors technique for improved performance under capacitive loads
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This paper presents a modified Cockcroft-Walton charge pump designed for driving capacitive or low current resistive loads. The proposed modification by using switched capacitors technique shows great improvement in output voltage levels that it achieves, and

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AbstractThe design of CP-PLL is a difficult exercise because of the wide range of applications and the complexity of modelling. As shown in a good behavioural model of the second order CP-PLL is the event driven model proposed in. The eventdriven model

Improved Charge Pump for Capacitor Discharge Applications
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All materials contained within the thesis, including without limitation text, logos, icons, photographs and other artwork, is copyright material of Universiti Putra Malaysia unless otherwise stated. Use may be made of any material contained within the thesis for non

2.7 V to 38V VIN range low noise 250mA buckboost charge pump converter
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The LTC3245 achieves efficiency of 80% when delivering 5V, 100mA from a 12V source, significantly higher efficiency than an LDO, making it possible to avoid the space and cost requirements of an LDO with a heat sink. The LTC3245 is available in an exposed pad

Improved charge pump circuit for high-voltage and energy applications using superposition theorem
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ABSTRACT: An improved charge pump circuit for high-voltage applications is presented. The advantage of this circuit is that its topology is simple, and it can produce a higher DC voltage and potential energy compared to conventional methods. The output is a quadratic

Designing of Charge Pump for Fast-Locking and Low-Power PLL
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AbstractThe specific property of fast locking of PLL is required in many clock and data recovery circuits. Many researchers, ,have tried to reduce this locking time but at the expense of power, phase noise and jitter. This paper presented a PLL with redesigning of

Design and implementation of modified charge pump for phase locked loop
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Abstract–A PLL is a closed loop system that locks the phase of an output signal to an input reference signal. The termlockrefers to a constant or zero phase difference between two signals. The components of PLL are the Phase Frequency Detector (PFD), the charge pump

Design of a Charge Pump PLL for LVDS SerDes
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AbstractA charge pump PLL for low-voltage differential signaling (LVDS) serializer/deserializer (SerDes) is presented. A proposed charge pump can greatly reduced non-ideal effects, and a novel four-stage differential VCO using self-biasing improves overall

LVPLL with MCSS Charge Pump in 90nm CMOS for SoCs
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Abstract-A Low voltage Power Efficient Phase Locked Loop is designed for SoCs. A MCSS Charge Pump is introduced to reduce leakage current and current mismatch. In order to achieve wide tuning range at low VCO gain Kvco. A Low voltage VCO (LV-VCO) for low

A precise systemC-AMS model for charge pump phase lock loop verified by its CMOS
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AbstractSystemC-AMS as an extension of SystemC provides the essential capability to describe a mixed-signal heterogeneous system, so that a virtual-prototype model can be generated to help analyze a whole mixed-signal system and further guide the circuit design.

Development of a Variable Roller Pump and Evaluation of Its Power Saving Potential as a Charge Pump in Hydrostatic Drivetrains
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The actual mobile machinery market indicates a lot of global trends but one trend is stable, the trend of focusing on ownership costs minimization. It is caused by many factors, from which two are the most important. The first one is simply fuel cost. The second factor is the

A regulated, charge pump CMOS DC/DC converter for low-power applications
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Abstract A regulated, low-power charge pump DC/DC converter implemented in CMOS technology has been designed and extensively simulated in HSPICE. The charge pump circuit is able to generate both positive and negative voltages. The converter consists of a

A low power prescaler, phase frequency detector, and charge pump for a 12 ghz frequency synthesizer
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A low power implementation of a CMOS frequency synthesizer at 12 GHz is an important step to improve the efficiency of a wireless transceiver in this frequency band. Since synthesizers are often employed as reference frequency sources such as local oscillators for

Charge Pump Loop Filter and VCO for Phase Lock Loop Using 0.18m CMOS Technology
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Abstract: This paper presents a Low power charge pump second order low pass filter and voltage controlled oscillator for low power phase lock loop. The paper contains the detailed circuit diagram of charge pump loop filter and voltage control oscillator with 1.8 v power

Energy harvesting applications for Low Voltage Dynamic CTS CMOS Charge Pump
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AbstractThis paper brings a detailed analysis and comparison of several charge pumps topologies that have not been optimized yet in order to make a relevant comparison of main parameters. The charge pumps were designed in a standard 90nm CMOS technology.

CMOS Voltage Reference Design using Variable-Voltage Charge Pump Circuit
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CMOS Voltage Reference Design using Variable-Voltage Charge Pump Circuit VLSI circuits require a precise and stable reference supply voltage circuit. A large range of voltage

Analysis and design of an exponential charge pump
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Abstract: Article Preview Article Preview This paper analyzed efficiency performance of two most popular charge pumps: Linear Dickson charge pump and the Exponential Dickson charge pump . The analysis result indicated that in a certain range, exponential charge pump

Charge Pump for Negative High Voltage Generation with Variable Voltage Gain
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Abstract: In this letter, a new cross-coupled charge pump for negative high voltage generation has been proposed. The problem of shoot-through current in the conventional cross-coupled charge pump is solved by a four clock phase scheme. By switching the power

Low Voltage Charge Pump Circuit Using 0.18m CMOS Technology
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An enhanced charge pump circuit utilizing charge-transfer-switch (CTS) to direct charge flow with improved voltage pumping gain is proposed in this paper. The diode configured output stage limitation is managed through the pumping of output stage by the clock of improved

Charge Pump Circuit design for Low Input Voltage
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Abstract In this paper, it is a proposal for a charge pump circuit design techniques for boosting the low voltage obtained from energy harvest techniques such as thermoelectric elements. In order to boost the low voltage, it did attempt to minimize the impact of high on-

Fast Charge Pump Circuit for PLL Using 50 nm CMOS Technology
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Abstract: PLL being a mixed signal circuit involves design challenge at high frequency. This work analyses the design of a mixed signal phase locked loop for faster phase and frequency locking. The performance of charge pumps depends heavily on the ability to

Charge Pump Modulated VCO for a Low Power UWB-FM Transmitter
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AbstractA modulated VCO in 90nm CMOS for low-power ultrawideband frequency modulation (UWB-FM) schemes is presented. By controlling the sensitive node in an inverter ring oscillator a wide and linear tuning range covering the available UWB spectrum, 3-

Dynamics of Parallel-Type and Serial-Type Charge Pump Circuits for High Voltage Generation
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Abstract This paper describes the dynamics of Dickson-type (parallel-type) charge pump circuits as well as serial-type (switched-capacitor-type) charge pump circuits for high voltage generation. We derive several formulas for their energy dissipation, node voltage, and

A CMOS charge pump circuit with short turn-on time for low-spur PLL synthesizers
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AbstractA charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can

Piezoelectric transformer based continuous-conduction-mode voltage source charge pump power factor correction electronic ballast
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Abstract This paper presents the piezoelectric transformer (PT) based continuous- conduction-mode (CCM) voltage source (VS) charge pump (CP) power factor correction (PFC) electronic ballast. By replacing LC resonant tank and transformer in the conventional

Reduction of peak input currents during charge pump boosting in integrated high-voltage generators
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Abstract:-This paper describes two methods for the reduction of the peak input current during the boosting of Dickson charge pumps. One of the methods is implemented in the fully integrated Dickson charge pumps of a high-voltage display driver chip for smart-card Abstract: A miilli-la:-er modeling approach is proposed in this paper for creating beliaviord models of Charge-Pomp Phase-Locked Loops. wldcli offers great flexibility of tnding off between the simulation speed and; iccuncy. Also the approach allorvs time doiiiain noise

A Charge Pump that Generates Negative High Voltage with Variable Voltage Gain
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Abstract A cross-coupled structure based charge pump that generates negative high voltages was developed. The problem of shoot-through current is solved by a four clock phase scheme. By switching the power supply to each stage based on the supply voltage, a

Charge pump phase-locked loops and full wave rectifiers for reachability analysis (benchmark proposal)
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Abstract Analog-mixed signal (AMS) circuits are widely used in various mission-critical applications necessitating their formal verification prior to implementation. We consider modeling two AMS circuits as hybrid automata, particularly a charge pump phase-locked Abstract: Article Preview Article Preview This paper describes a bipolar output DC-DC converter that uses a single inductor for size andcost reduction. We propose a timing diagram for a charge pump circuit which generates the negative outputvoltage, and present

High voltage charge pump circuit for an ion mobility spectrometer
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I thank the Environmental Protection Agency (EPA) for funding the sensor project because of which I could complete this work successfully. My very special thanks to my advisor, Dr. Jacob Baker without whom this project would not be a success. I also thank the Project

A Dual-rail Charge Pump Bias Circuit for Avalanche Photodiodes
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AbstractIn this paper, a dual-rail charge pump bias circuit for avalanche photodiodes is presented. The proposed circuit was fabricated and measured on a printed circuit board (PCB). Experimental measurements show that it is capable of providing up to 50 V bias

Low Power CMOS Start-Up Charge Pump with Power Gating Technique
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Abstract: CMOS is used to construct the integrated circuits with low level of static leakage. With this low level leakage we are designing all the transistor circuits in CMOS logic. To control this static leakage in the circuits the supply voltage is a major concern. Here the step-

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Abstract: The success of integrated renewable energy sources in mobile computing systems highly depends on low cost, low area, and efficient power conversion schemes. Various boost implementations have thus been analyzed in this work for suitability to the application

Optimum Design of Charge Pump Circuits Using Genetic Algorithm
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AbstractIntegrated charge pump circuits are power converter used to obtain a different dc levels. The most important performance parameters that effect the operation of these circuits may include voltage gain, ripple voltage, conversion efficiency, power consumption, and the

A High Efficiency and Low Ripple Cross-Coupled Charge Pump Circuit
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Abstract: A fully integrated cross-coupled charge pump circuit with four-clock signals and a new method of body bias have been proposed. The new clock scheme eliminates all of the reversion power loss and reduces the ripple voltage. In addition, the largest voltage

Phase-Locked Loop with High stability against process variation and Gain-Boosting Charge Pump for Current Matching characteristics
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Abstract The charge pump (CP) circuit is a key element in a phaselocked loop (PLL). Its function is to transform the Up and Down signals from the phase/frequency detector into current. In CMOS CPs, which have Up and Down switches made of p-channel MOS and n-

A Fast-Response Charge Pump Gate Driver Applied to Linear Regulation
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This paper presents a compact charge pump gate driver (CPGD) that dynamically adjusts the driving voltage VGS_SW of power switches, following stringent load transients in amplitude and duration. Owing to its simple topology, the CPGD responsively sustains

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ABSTRACT This paper presents a new Charge Pump current limiter scheme. The current limitation system and the Driver equations will be presented and described. Simulations have been done for a typical case, as well as taking temperature and process variation into

Low Mismatch Wide Swing Charge Pump for PLLs
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Abstract An accurate, wide output swing, low voltage charge pump is proposed. It is based on a second generation current conveyor which is used to equate charging and discharging currents. A low voltage enhanced current mirror ensures matching between nominal and

The RF charge pump technique for measuring the interface state density on leaky dielectrics
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AbstractIn this work the RF charge pump technique is presented. It is shown that this technique can provide charge pump data of devices that have a leakage current too high for classical charge pump measurements. The methodology of accurately performing RF

Design and Analysis of Charge Pump for PLL Applications using 70nm Technology
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AbstractThis paper presents a CMOS Charge Pump using 70nm technology that operates at 0.7 V. The proposed circuit has simple symmetric structure and provides more stable operation deals with different approaches to design a high speed CMOS charge pump

A Study of a New Methodology for 2-Type 3-Order Charge Pump PLLs
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We proposed a new methodology for 2-type 3-order Charge PumpPLLs (CP-PLLs) utilizing loop gain optimization, for which PLL operation are divided into 2-modes, pullin and lock modes. We derived a set of equations which ensure the stability of the PLLs by avoiding

A topological charge pump
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Figure 1| Illustration of the superlattice and pumping scheme. a, A superlattice created by superimposing two lattices (red and grey lines) with periodicities dL and dS (dL= 2dS). J1 and J2 represent the tunnel couplings of the double-wells, and is the energy offset

Improved Charge Pump PLL using Dual-PFDs and Adaptive Loop Filter
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Abstract-Phase-locked loops (PLLs) are widely used in many applications, including frequency syntheses, clock and data recovery circuits (CDRs), and clock generators. Almost all PLL applications require low jitter and fast lock time. As such, this paper proposes a

Multimode Power Gating Architecture And Energy Storage Using Charge Pump Circuit
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ABSTRACT: Multithreshold cmos mainly used to reduce the leakage power during long periods of inactivity mode. power gating scheme used to support multiple power off modes and reduce the leakage power at the time of short periods of inactivity. Power gating used to

A Reduced-Ripple PMOS Charge Pump Circuit with Small Filtering Capacitors
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The charge pump (CP) circuit has been widely used in MEMS, flash memories, EEPROM, and so on. It is usually used as a simple on-die DC-DC voltage converter, to provide voltages higher than the supply voltage. Most of the charge pumps are based on the AbstractIn this paper, an advanced layout scheme of an integrated capacitor is presented which improves the efficiency of a poly-poly capacitor based voltage doubler charge pump . The main losses in voltage doubler charge pumps are mathematically described and the

Fast Charge Pump Phase Locked Loop with a BBFC: A Numerical Confirmation
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Abstract. Speeding up a synthesizer locking process can be considered as speeding up the charge pump PLL. Several methods have been introduced to increase the speed of the locking process. One way to achieve fast locking is to use a bangbang frequency

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