rtl-register-transfer level-vlsi


register-transfer level (RTL) is a design abstraction which models digital circuit

Power reduction through RTL clock gating
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ABSTRACT This paper describes a design methodology for reducing ASIC power consumption through use of the RTL clock gating feature in Synopsys Power Compiler. This feature causes inactive clocked elements to have clock gating logic automatically inserted

Efficient sequential ATPG for functional RTL circuits
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Abstract We present an efficient register-transfer level automatic test pattern generation (ATPG) algorithm. First, our ATPG generates a series of sequential justification and propagation paths for each RTL primitive via a deterministic branch-and-bound search

C-based Interactive RTL Design Methodology
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Abstract Much effort in RTL design has been devoted to developingpush-buttontypes of tools. However, given the highly complex nature of RTL design, interactive design space exploration with assistance of tools and algorithms can be more effective. In this report, we

Seismicity pattern changes prior to large earthquakes-An approach of the RTL algorithm
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A statistical method, which is called the Region-Time-Length ( RTL ) algorithm and takes into account information such as magnitude, occurrence time and place of earthquakes, was applied to earthquake data to investigate seismicity pattern changes prior to large

Methodology for repeater insertion management in the RTL layout, floorplan and fullchip timing databases of the Itanium microprocessor
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Page 1. 99 Methodology for Repeater Insertion Management in the RTL Layout, Floorplan and Fullchip Timing Databases of the Itanium Microprocessor Rory McInerney Kurt Leeper Troy Hill Intel Corp. Intel Corp. Intel Corp. SC12-408 SC12-405 RA2-350Intel Corp. Intel Corp. Intel

Red thermoluminescence ( RTL ) in volcanic quartz: development of a high sensitivity detection system and some preliminary ndings
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Abstract: As part of a general study exploring the suitability of the RTL of quartz for dating volcanic events, a modied RisaI Reader apparatus has been assembled and tested. Modication consisted of an alternative, cooled photomultiplier, and the incorporation of

RTL Coding Styles That Yield Simulation and Synthesis Mismatches
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ABSTRACT This paper details, with examples, Verilog coding styles that will cause a mismatch between preand post-synthesis simulations. Frequently, these mismatches are not discovered until after silicon has been generated, and thus require the design to be re-

Formal verification of floating-point RTL at AMD using the ACL2 theorem prover
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Abstract-We describe a methodology for the formal verification of the correctness, including IEEE-compliance, of register-transfer level models of floating-point hardware designs, and its application to the floating-point units of a series of commercial microprocessors produced

RTL : reduced texture spectrum with lag value based image retrieval for medical images
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Abstract Medical images have become the recent key investigation tools for medical diagnosis and treatment planning. Due to the advent of digital imaging the need of data storage and retrieval of medical images increased rapidly. Some difficulties in retrieving the

Optimized RTL design and implementation of LZW algorithm for high bandwidth applications
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Abstract. This paper presents a high-speed low-complexity Register Transfer Logic ( RTL ) design and implementation of the lossless Lempel-Ziv-Welch (LZW) algorithm on Xilinx Virtex II device family for High Bandwidth Applications. Comparative analysis of the

RTL emulation: the next leap in system verification
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To answer the second question, semiconductor fabrications can now put millions of logic gates on a single chip using deep sub-micron technology. This rapid increase in the complexity of chips and systems has outstripped traditional verification techniques. This is

Guest editors introduction: RTL to GDSII-from foilware to standard practice
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University of California, San Diego ically correct or 100% layout-rule correct if it doesnt meet timing constraints. Traditionally, static timing analysis was run at the beginning of the process at a milestone called RTL handoff, and at the end of the flow at a mask sign-off

Automatic generation of fault tolerant VHDL designs in RTL
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Abstract Fault Tolerance (FT) is an important issue in electronic devices. Detecting and even correcting internal faults during normal operation makes possible the usage of these circuits in critical applications. FT has been taken into account for many years during design process

A FSM extractor for HDL description at RTL level
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Abstract Due to the increasing complexity of modern circuit designs, HDL based design methodology is getting popular. Because Finite State Machines (FSMs) and datapaths have significantly different properties, dealing them with two different ways is a trend of many CAD



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